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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>E:\HL\hl_laser\impl\gwsynthesis\hl_laser.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>E:\HL\hl_laser\src\hl_laser.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>E:\HL\hl_laser\src\hl_laser.sdc</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.06-1</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1N-UV2MG132C7/I6</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1N-2B</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Apr 24 13:48:24 2025
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 3.135V 85C C7/I6</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 3.465V 0C C7/I6</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>4088</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>3403</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>3</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>0</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>1</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>clk_in</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>clk_in </td>
</tr>
<tr>
<td>sys_clk</td>
<td>Generated</td>
<td>10.000</td>
<td>100.000
<td>0.000</td>
<td>5.000</td>
<td>clk_in </td>
<td>clk_in</td>
<td>pll/pllo_inst/CLKOUTA </td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Base</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td></td>
<td></td>
<td>gw_gao_inst_0/tck_ibuf/I </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>sys_clk</td>
<td>100.000(MHz)</td>
<td>100.119(MHz)</td>
<td>9</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>tck_pad_i</td>
<td>20.000(MHz)</td>
<td>164.515(MHz)</td>
<td>3</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of clk_in!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>clk_in</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>clk_in</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>sys_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.012</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
<td>laser_ctrl/ld1_pwr_13_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.692</td>
</tr>
<tr>
<td>2</td>
<td>0.363</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
<td>laser_ctrl/ld1_pwr_11_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.341</td>
</tr>
<tr>
<td>3</td>
<td>0.567</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>7.089</td>
</tr>
<tr>
<td>4</td>
<td>0.602</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/blue_en_delay_cnt_1_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.366</td>
</tr>
<tr>
<td>5</td>
<td>0.794</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_1_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.173</td>
</tr>
<tr>
<td>6</td>
<td>0.818</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_1_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.150</td>
</tr>
<tr>
<td>7</td>
<td>0.818</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_4_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.150</td>
</tr>
<tr>
<td>8</td>
<td>0.818</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_5_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.150</td>
</tr>
<tr>
<td>9</td>
<td>0.818</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_6_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.150</td>
</tr>
<tr>
<td>10</td>
<td>0.824</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_3_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.144</td>
</tr>
<tr>
<td>11</td>
<td>0.829</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.562</td>
</tr>
<tr>
<td>12</td>
<td>0.850</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_3_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.118</td>
</tr>
<tr>
<td>13</td>
<td>0.850</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_4_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.118</td>
</tr>
<tr>
<td>14</td>
<td>0.850</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_5_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.118</td>
</tr>
<tr>
<td>15</td>
<td>0.850</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_6_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.118</td>
</tr>
<tr>
<td>16</td>
<td>0.850</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/en_delay_cnt_7_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.118</td>
</tr>
<tr>
<td>17</td>
<td>0.858</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
<td>laser_ctrl/ld1_pwr_12_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>8.846</td>
</tr>
<tr>
<td>18</td>
<td>0.874</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/blue_en_delay_cnt_7_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>9.093</td>
</tr>
<tr>
<td>19</td>
<td>0.878</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.512</td>
</tr>
<tr>
<td>20</td>
<td>0.882</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.509</td>
</tr>
<tr>
<td>21</td>
<td>1.054</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.337</td>
</tr>
<tr>
<td>22</td>
<td>1.075</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.316</td>
</tr>
<tr>
<td>23</td>
<td>1.075</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D</td>
<td>tck_pad_i:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>2.283</td>
<td>6.316</td>
</tr>
<tr>
<td>24</td>
<td>1.091</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_0_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>8.877</td>
</tr>
<tr>
<td>25</td>
<td>1.091</td>
<td>laser_ctrl/cnt_1us_0_s0/Q</td>
<td>laser_ctrl/sw_delay_cnt_2_s0/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>10.000</td>
<td>0.000</td>
<td>8.877</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;">
<td>1</td>
<td>-0.931</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D</td>
<td>sys_clk:[R]</td>
<td>tck_pad_i:[R]</td>
<td>0.000</td>
<td>-1.830</td>
<td>0.929</td>
</tr>
<tr>
<td>2</td>
<td>0.355</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.418</td>
</tr>
<tr>
<td>3</td>
<td>0.355</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.418</td>
</tr>
<tr>
<td>4</td>
<td>0.392</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[12]</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.448</td>
</tr>
<tr>
<td>5</td>
<td>0.410</td>
<td>laser_ctrl/blue_pwr_0_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s4/DI[0]</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.421</td>
</tr>
<tr>
<td>6</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_20_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>7</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_24_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>8</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_26_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>9</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_31_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>10</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_32_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>11</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_81_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>12</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_109_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>13</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_116_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>14</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_135_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_134_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>15</td>
<td>0.422</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_145_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.422</td>
</tr>
<tr>
<td>16</td>
<td>0.423</td>
<td>laser_ctrl/red_r1_s0/Q</td>
<td>laser_ctrl/red_r2_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.423</td>
</tr>
<tr>
<td>17</td>
<td>0.425</td>
<td>laser_ctrl/pwm_detect_inst/cycle_cnt_15_s0/Q</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_15_s1/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.425</td>
</tr>
<tr>
<td>18</td>
<td>0.428</td>
<td>laser_ctrl/en_r1_s0/Q</td>
<td>laser_ctrl/en_r2_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.428</td>
</tr>
<tr>
<td>19</td>
<td>0.437</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s2/Q</td>
<td>laser_ctrl/power_r0_0_s5/CE</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.448</td>
</tr>
<tr>
<td>20</td>
<td>0.443</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.443</td>
</tr>
<tr>
<td>21</td>
<td>0.443</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_79_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.443</td>
</tr>
<tr>
<td>22</td>
<td>0.445</td>
<td>laser_ctrl/pwr_buf_1_s0/Q</td>
<td>laser_ctrl/ld1_pwr_buf_1_s0/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.445</td>
</tr>
<tr>
<td>23</td>
<td>0.524</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1/Q</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.524</td>
</tr>
<tr>
<td>24</td>
<td>0.524</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1/Q</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1/D</td>
<td>sys_clk:[R]</td>
<td>sys_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.524</td>
</tr>
<tr>
<td>25</td>
<td>0.524</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0/D</td>
<td>tck_pad_i:[R]</td>
<td>tck_pad_i:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.524</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>2</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>3</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>4</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>5</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>6</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>7</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>8</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>9</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>10</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>11</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>12</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>13</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>14</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>15</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>16</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>17</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>18</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>19</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>20</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>21</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>22</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>23</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>24</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
<tr>
<td>25</td>
<td>2.659</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>5.000</td>
<td>0.014</td>
<td>2.295</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>4.283</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-5.000</td>
<td>-1.822</td>
<td>1.147</td>
</tr>
<tr>
<td>2</td>
<td>4.691</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-5.000</td>
<td>-1.822</td>
<td>1.554</td>
</tr>
<tr>
<td>3</td>
<td>4.691</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>tck_pad_i:[R]</td>
<td>-5.000</td>
<td>-1.822</td>
<td>1.554</td>
</tr>
<tr>
<td>4</td>
<td>5.847</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>0.850</td>
</tr>
<tr>
<td>5</td>
<td>6.144</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.147</td>
</tr>
<tr>
<td>6</td>
<td>6.144</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.147</td>
</tr>
<tr>
<td>7</td>
<td>6.144</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.147</td>
</tr>
<tr>
<td>8</td>
<td>6.144</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.147</td>
</tr>
<tr>
<td>9</td>
<td>6.144</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.147</td>
</tr>
<tr>
<td>10</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>11</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>12</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>13</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>14</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>15</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>16</td>
<td>6.148</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.151</td>
</tr>
<tr>
<td>17</td>
<td>6.339</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.342</td>
</tr>
<tr>
<td>18</td>
<td>6.355</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.359</td>
</tr>
<tr>
<td>19</td>
<td>6.355</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.359</td>
</tr>
<tr>
<td>20</td>
<td>6.355</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.359</td>
</tr>
<tr>
<td>21</td>
<td>6.355</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.359</td>
</tr>
<tr>
<td>22</td>
<td>6.355</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.359</td>
</tr>
<tr>
<td>23</td>
<td>6.365</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.368</td>
</tr>
<tr>
<td>24</td>
<td>6.365</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.368</td>
</tr>
<tr>
<td>25</td>
<td>6.365</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
<td>sys_clk:[F]</td>
<td>sys_clk:[R]</td>
<td>-5.000</td>
<td>0.008</td>
<td>1.368</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
<tr>
<td>2</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
<tr>
<td>3</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0</td>
</tr>
<tr>
<td>4</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
<tr>
<td>5</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_133_s0</td>
</tr>
<tr>
<td>6</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0</td>
</tr>
<tr>
<td>7</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0</td>
</tr>
<tr>
<td>8</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s</td>
</tr>
<tr>
<td>9</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>laser_ctrl/pwm_detect_inst/pwm_high_15_s1</td>
</tr>
<tr>
<td>10</td>
<td>4.016</td>
<td>4.942</td>
<td>0.926</td>
<td>Low Pulse Width</td>
<td>sys_clk</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_0_s1</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.012</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.872</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/ld1_pwr_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C11[3][A]</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R18C11[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
</tr>
<tr>
<td>1.608</td>
<td>1.088</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[1][B]</td>
<td>laser_ctrl/n726_s/I0</td>
</tr>
<tr>
<td>2.383</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n726_s/COUT</td>
</tr>
<tr>
<td>2.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[2][A]</td>
<td>laser_ctrl/n725_s/CIN</td>
</tr>
<tr>
<td>2.800</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s/SUM</td>
</tr>
<tr>
<td>3.755</td>
<td>0.955</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[1][B]</td>
<td>laser_ctrl/n725_s0/I0</td>
</tr>
<tr>
<td>4.529</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s0/COUT</td>
</tr>
<tr>
<td>4.529</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[2][A]</td>
<td>laser_ctrl/n724_s0/CIN</td>
</tr>
<tr>
<td>4.947</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n724_s0/SUM</td>
</tr>
<tr>
<td>5.543</td>
<td>0.596</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][A]</td>
<td>laser_ctrl/n732_s/I0</td>
</tr>
<tr>
<td>6.317</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n732_s/COUT</td>
</tr>
<tr>
<td>6.317</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][B]</td>
<td>laser_ctrl/n731_s/CIN</td>
</tr>
<tr>
<td>6.359</td>
<td>0.042</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n731_s/COUT</td>
</tr>
<tr>
<td>6.359</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[1][A]</td>
<td>laser_ctrl/n730_s/CIN</td>
</tr>
<tr>
<td>6.401</td>
<td>0.042</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[1][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n730_s/COUT</td>
</tr>
<tr>
<td>7.660</td>
<td>1.258</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C16[3][B]</td>
<td>laser_ctrl/n738_s2/I2</td>
</tr>
<tr>
<td>8.254</td>
<td>0.594</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R18C16[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n738_s2/F</td>
</tr>
<tr>
<td>8.564</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C17[3][A]</td>
<td>laser_ctrl/gw_add_dLut_ld1_pwr_13_s0/I0</td>
</tr>
<tr>
<td>9.028</td>
<td>0.464</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C17[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_dLut_ld1_pwr_13_s0/F</td>
</tr>
<tr>
<td>9.872</td>
<td>0.844</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOR17[A]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_13_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR17[A]</td>
<td>laser_ctrl/ld1_pwr_13_s0/CLK</td>
</tr>
<tr>
<td>9.884</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOR17[A]</td>
<td>laser_ctrl/ld1_pwr_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.300, 44.368%; route: 5.052, 52.128%; tC2Q: 0.340, 3.504%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.363</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.522</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/ld1_pwr_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C11[3][A]</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R18C11[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
</tr>
<tr>
<td>1.608</td>
<td>1.088</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[1][B]</td>
<td>laser_ctrl/n726_s/I0</td>
</tr>
<tr>
<td>2.383</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n726_s/COUT</td>
</tr>
<tr>
<td>2.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[2][A]</td>
<td>laser_ctrl/n725_s/CIN</td>
</tr>
<tr>
<td>2.800</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s/SUM</td>
</tr>
<tr>
<td>3.755</td>
<td>0.955</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[1][B]</td>
<td>laser_ctrl/n725_s0/I0</td>
</tr>
<tr>
<td>4.529</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s0/COUT</td>
</tr>
<tr>
<td>4.529</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[2][A]</td>
<td>laser_ctrl/n724_s0/CIN</td>
</tr>
<tr>
<td>4.947</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n724_s0/SUM</td>
</tr>
<tr>
<td>5.543</td>
<td>0.596</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][A]</td>
<td>laser_ctrl/n732_s/I0</td>
</tr>
<tr>
<td>6.317</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n732_s/COUT</td>
</tr>
<tr>
<td>6.317</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][B]</td>
<td>laser_ctrl/n731_s/CIN</td>
</tr>
<tr>
<td>6.734</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n731_s/SUM</td>
</tr>
<tr>
<td>6.738</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td>laser_ctrl/n740_s1/I0</td>
</tr>
<tr>
<td>7.553</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n740_s1/F</td>
</tr>
<tr>
<td>8.149</td>
<td>0.596</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C18[3][A]</td>
<td>laser_ctrl/gw_add_dLut_ld1_pwr_11_s0/I0</td>
</tr>
<tr>
<td>8.913</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C18[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_dLut_ld1_pwr_11_s0/F</td>
</tr>
<tr>
<td>9.522</td>
<td>0.608</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOR18[B]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR18[B]</td>
<td>laser_ctrl/ld1_pwr_11_s0/CLK</td>
</tr>
<tr>
<td>9.884</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOR18[B]</td>
<td>laser_ctrl/ld1_pwr_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 5.154, 55.174%; route: 3.848, 41.190%; tC2Q: 0.340, 3.636%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.567</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.552</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.119</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.555</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>7.875</td>
<td>0.321</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0</td>
</tr>
<tr>
<td>8.662</td>
<td>0.786</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F</td>
</tr>
<tr>
<td>9.552</td>
<td>0.891</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td>10.119</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.942, 41.500%; route: 3.807, 53.708%; tC2Q: 0.340, 4.791%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.602</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.547</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/blue_en_delay_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.181</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C17[3][B]</td>
<td>laser_ctrl/n535_s1/I0</td>
</tr>
<tr>
<td>7.645</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C17[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n535_s1/F</td>
</tr>
<tr>
<td>7.649</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C17[1][B]</td>
<td>laser_ctrl/gw_add_ceLut_blue_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.409</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_blue_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.547</td>
<td>1.138</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C17[1][A]</td>
<td style=" font-weight:bold;">laser_ctrl/blue_en_delay_cnt_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C17[1][A]</td>
<td>laser_ctrl/blue_en_delay_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C17[1][A]</td>
<td>laser_ctrl/blue_en_delay_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.363, 35.903%; route: 5.664, 60.470%; tC2Q: 0.340, 3.626%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.794</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.354</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.354</td>
<td>0.586</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C18[3][A]</td>
<td>laser_ctrl/en_delay_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C18[3][A]</td>
<td>laser_ctrl/en_delay_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 40.760%; route: 5.095, 55.538%; tC2Q: 0.340, 3.702%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.818</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.330</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_1_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>laser_ctrl/sw_delay_cnt_1_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[3][A]</td>
<td>laser_ctrl/sw_delay_cnt_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 37.035%; route: 5.421, 59.253%; tC2Q: 0.340, 3.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.818</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.330</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>laser_ctrl/sw_delay_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[1][B]</td>
<td>laser_ctrl/sw_delay_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 37.035%; route: 5.421, 59.253%; tC2Q: 0.340, 3.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.818</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.330</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>laser_ctrl/sw_delay_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[2][A]</td>
<td>laser_ctrl/sw_delay_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 37.035%; route: 5.421, 59.253%; tC2Q: 0.340, 3.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.818</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.330</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.330</td>
<td>0.528</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>laser_ctrl/sw_delay_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C12[2][B]</td>
<td>laser_ctrl/sw_delay_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 37.035%; route: 5.421, 59.253%; tC2Q: 0.340, 3.712%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.824</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.325</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.325</td>
<td>0.523</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C11[3][A]</td>
<td>laser_ctrl/sw_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C11[3][A]</td>
<td>laser_ctrl/sw_delay_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 37.058%; route: 5.416, 59.228%; tC2Q: 0.340, 3.714%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.829</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.026</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>8.211</td>
<td>0.628</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n867_s1/I3</td>
</tr>
<tr>
<td>9.026</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n867_s1/F</td>
</tr>
<tr>
<td>9.026</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.998, 45.688%; route: 3.224, 49.136%; tC2Q: 0.340, 5.176%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.298</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[1][B]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_3_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[1][B]</td>
<td>laser_ctrl/en_delay_cnt_3_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C19[1][B]</td>
<td>laser_ctrl/en_delay_cnt_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 41.009%; route: 5.039, 55.266%; tC2Q: 0.340, 3.725%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.298</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[2][A]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_4_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[2][A]</td>
<td>laser_ctrl/en_delay_cnt_4_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C19[2][A]</td>
<td>laser_ctrl/en_delay_cnt_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 41.009%; route: 5.039, 55.266%; tC2Q: 0.340, 3.725%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.298</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[2][B]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_5_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[2][B]</td>
<td>laser_ctrl/en_delay_cnt_5_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C19[2][B]</td>
<td>laser_ctrl/en_delay_cnt_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 41.009%; route: 5.039, 55.266%; tC2Q: 0.340, 3.725%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.298</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_6_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[3][A]</td>
<td>laser_ctrl/en_delay_cnt_6_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C19[3][A]</td>
<td>laser_ctrl/en_delay_cnt_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 41.009%; route: 5.039, 55.266%; tC2Q: 0.340, 3.725%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.850</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.298</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.164</td>
<td>0.968</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td>laser_ctrl/n314_s1/I0</td>
</tr>
<tr>
<td>7.978</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C19[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n314_s1/F</td>
</tr>
<tr>
<td>7.982</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C19[3][B]</td>
<td>laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.769</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C19[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.298</td>
<td>0.530</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[1][A]</td>
<td style=" font-weight:bold;">laser_ctrl/en_delay_cnt_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C19[1][A]</td>
<td>laser_ctrl/en_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R4C19[1][A]</td>
<td>laser_ctrl/en_delay_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.739, 41.009%; route: 5.039, 55.266%; tC2Q: 0.340, 3.725%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.858</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.026</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.884</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/ld1_pwr_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C11[3][A]</td>
<td>laser_ctrl/ld1_pwr_buf_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>4</td>
<td>R18C11[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_buf_0_s0/Q</td>
</tr>
<tr>
<td>1.608</td>
<td>1.088</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[1][B]</td>
<td>laser_ctrl/n726_s/I0</td>
</tr>
<tr>
<td>2.383</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n726_s/COUT</td>
</tr>
<tr>
<td>2.383</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C17[2][A]</td>
<td>laser_ctrl/n725_s/CIN</td>
</tr>
<tr>
<td>2.800</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C17[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s/SUM</td>
</tr>
<tr>
<td>3.755</td>
<td>0.955</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[1][B]</td>
<td>laser_ctrl/n725_s0/I0</td>
</tr>
<tr>
<td>4.529</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n725_s0/COUT</td>
</tr>
<tr>
<td>4.529</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C16[2][A]</td>
<td>laser_ctrl/n724_s0/CIN</td>
</tr>
<tr>
<td>4.947</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C16[2][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n724_s0/SUM</td>
</tr>
<tr>
<td>5.543</td>
<td>0.596</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][A]</td>
<td>laser_ctrl/n732_s/I0</td>
</tr>
<tr>
<td>6.317</td>
<td>0.774</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n732_s/COUT</td>
</tr>
<tr>
<td>6.317</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[0][B]</td>
<td>laser_ctrl/n731_s/CIN</td>
</tr>
<tr>
<td>6.359</td>
<td>0.042</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n731_s/COUT</td>
</tr>
<tr>
<td>6.359</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R18C15[1][A]</td>
<td>laser_ctrl/n730_s/CIN</td>
</tr>
<tr>
<td>6.776</td>
<td>0.417</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[1][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/n730_s/SUM</td>
</tr>
<tr>
<td>6.780</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td>laser_ctrl/n739_s1/I0</td>
</tr>
<tr>
<td>7.244</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C15[2][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n739_s1/F</td>
</tr>
<tr>
<td>7.966</td>
<td>0.722</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C18[3][B]</td>
<td>laser_ctrl/gw_add_dLut_ld1_pwr_12_s0/I0</td>
</tr>
<tr>
<td>8.430</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R18C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_dLut_ld1_pwr_12_s0/F</td>
</tr>
<tr>
<td>9.026</td>
<td>0.596</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOR17[B]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOR17[B]</td>
<td>laser_ctrl/ld1_pwr_12_s0/CLK</td>
</tr>
<tr>
<td>9.884</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOR17[B]</td>
<td>laser_ctrl/ld1_pwr_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 4.545, 51.376%; route: 3.961, 44.784%; tC2Q: 0.340, 3.839%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.874</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.274</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/blue_en_delay_cnt_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.181</td>
<td>0.984</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C17[3][B]</td>
<td>laser_ctrl/n535_s1/I0</td>
</tr>
<tr>
<td>7.645</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R5C17[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n535_s1/F</td>
</tr>
<tr>
<td>7.649</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R5C17[1][B]</td>
<td>laser_ctrl/gw_add_ceLut_blue_en_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.409</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R5C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_blue_en_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.274</td>
<td>0.865</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C19[1][A]</td>
<td style=" font-weight:bold;">laser_ctrl/blue_en_delay_cnt_7_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C19[1][A]</td>
<td>laser_ctrl/blue_en_delay_cnt_7_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R5C19[1][A]</td>
<td>laser_ctrl/blue_en_delay_cnt_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.363, 36.979%; route: 5.391, 59.286%; tC2Q: 0.340, 3.735%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.878</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.976</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>8.211</td>
<td>0.628</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n868_s1/I2</td>
</tr>
<tr>
<td>8.976</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n868_s1/F</td>
</tr>
<tr>
<td>8.976</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.948, 45.274%; route: 3.224, 49.511%; tC2Q: 0.340, 5.215%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.882</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.973</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>8.208</td>
<td>0.625</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n870_s3/I3</td>
</tr>
<tr>
<td>8.973</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n870_s3/F</td>
</tr>
<tr>
<td>8.973</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.948, 45.298%; route: 3.221, 49.484%; tC2Q: 0.340, 5.218%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.054</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.800</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>8.191</td>
<td>0.608</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s1/I2</td>
</tr>
<tr>
<td>8.800</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s1/F</td>
</tr>
<tr>
<td>8.800</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.793, 44.074%; route: 3.204, 50.566%; tC2Q: 0.340, 5.360%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.075</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.779</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>7.965</td>
<td>0.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s1/I3</td>
</tr>
<tr>
<td>8.779</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n869_s1/F</td>
</tr>
<tr>
<td>8.779</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.998, 47.470%; route: 2.978, 47.153%; tC2Q: 0.340, 5.377%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.075</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.779</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.854</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.728</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.728</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.455</td>
<td>0.728</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>2.464</td>
<td>1.008</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK</td>
</tr>
<tr>
<td>2.803</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R9C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q</td>
</tr>
<tr>
<td>3.760</td>
<td>0.957</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/I0</td>
</tr>
<tr>
<td>4.521</td>
<td>0.760</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>R8C3[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s8/F</td>
</tr>
<tr>
<td>4.831</td>
<td>0.310</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R8C2[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/I1</td>
</tr>
<tr>
<td>5.440</td>
<td>0.609</td>
<td>tINS</td>
<td>RF</td>
<td>2</td>
<td>R8C2[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s6/F</td>
</tr>
<tr>
<td>6.769</td>
<td>1.328</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R14C6[3][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/I0</td>
</tr>
<tr>
<td>7.583</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>R14C6[3][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n864_s4/F</td>
</tr>
<tr>
<td>7.965</td>
<td>0.382</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n866_s1/I3</td>
</tr>
<tr>
<td>8.779</td>
<td>0.814</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n866_s1/F</td>
</tr>
<tr>
<td>8.779</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK</td>
</tr>
<tr>
<td>10.151</td>
<td>-0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1</td>
</tr>
<tr>
<td>9.854</td>
<td>-0.296</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.283</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.455, 59.066%; route: 1.008, 40.934%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 2.998, 47.470%; route: 2.978, 47.153%; tC2Q: 0.340, 5.377%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.091</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.058</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.058</td>
<td>0.256</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_0_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>laser_ctrl/sw_delay_cnt_0_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[0][A]</td>
<td>laser_ctrl/sw_delay_cnt_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 38.172%; route: 5.149, 58.002%; tC2Q: 0.340, 3.826%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.091</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.058</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/cnt_1us_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/sw_delay_cnt_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C12[3][A]</td>
<td>laser_ctrl/cnt_1us_0_s0/CLK</td>
</tr>
<tr>
<td>0.520</td>
<td>0.340</td>
<td>tC2Q</td>
<td>RF</td>
<td>9</td>
<td>R4C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/cnt_1us_0_s0/Q</td>
</tr>
<tr>
<td>1.969</td>
<td>1.448</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C14[3][B]</td>
<td>laser_ctrl/led_ctrl/n26_s2/I0</td>
</tr>
<tr>
<td>2.578</td>
<td>0.609</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>R7C14[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/led_ctrl/n26_s2/F</td>
</tr>
<tr>
<td>4.022</td>
<td>1.444</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R7C17[1][B]</td>
<td>laser_ctrl/cnt_1ms_9_s3/I2</td>
</tr>
<tr>
<td>4.787</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>24</td>
<td>R7C17[1][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/cnt_1ms_9_s3/F</td>
</tr>
<tr>
<td>5.432</td>
<td>0.645</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R8C18[3][B]</td>
<td>laser_ctrl/n201_s2/I1</td>
</tr>
<tr>
<td>6.196</td>
<td>0.765</td>
<td>tINS</td>
<td>FF</td>
<td>8</td>
<td>R8C18[3][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n201_s2/F</td>
</tr>
<tr>
<td>7.548</td>
<td>1.351</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td>laser_ctrl/n374_s1/I0</td>
</tr>
<tr>
<td>8.012</td>
<td>0.464</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R9C13[0][B]</td>
<td style=" background: #97FFFF;">laser_ctrl/n374_s1/F</td>
</tr>
<tr>
<td>8.016</td>
<td>0.004</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C13[3][A]</td>
<td>laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/I0</td>
</tr>
<tr>
<td>8.802</td>
<td>0.786</td>
<td>tINS</td>
<td>FR</td>
<td>8</td>
<td>R9C13[3][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/gw_add_ceLut_sw_delay_cnt_7_s0/F</td>
</tr>
<tr>
<td>9.058</td>
<td>0.256</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td style=" font-weight:bold;">laser_ctrl/sw_delay_cnt_2_s0/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>laser_ctrl/sw_delay_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R9C13[1][A]</td>
<td>laser_ctrl/sw_delay_cnt_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 3.389, 38.172%; route: 5.149, 58.002%; tC2Q: 0.340, 3.826%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-0.931</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>51.066</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>51.997</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>50.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK</td>
</tr>
<tr>
<td>50.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R5C7[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/Q</td>
</tr>
<tr>
<td>50.791</td>
<td>0.407</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/n4901_s0/I0</td>
</tr>
<tr>
<td>51.066</td>
<td>0.276</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/n4901_s0/F</td>
</tr>
<tr>
<td>51.066</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>50.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>50.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>51.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>51.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK</td>
</tr>
<tr>
<td>51.997</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td>51.997</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C8[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.276, 29.659%; route: 0.407, 43.765%; tC2Q: 0.247, 26.576%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.555</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.201</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C17[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R11C17[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q</td>
</tr>
<tr>
<td>0.555</td>
<td>0.171</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA</td>
</tr>
<tr>
<td>0.201</td>
<td>0.064</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[3]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.555</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.201</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C14[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R11C14[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q</td>
</tr>
<tr>
<td>0.555</td>
<td>0.171</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R10[2]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[2]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA</td>
</tr>
<tr>
<td>0.201</td>
<td>0.064</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[2]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.392</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.584</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.192</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>7</td>
<td>R12C6[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q</td>
</tr>
<tr>
<td>0.584</td>
<td>0.201</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[1]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/ADA[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R10[1]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA</td>
</tr>
<tr>
<td>0.192</td>
<td>0.056</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R10[1]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.201, 44.828%; tC2Q: 0.247, 55.172%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.410</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.558</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/blue_pwr_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C2[2][B]</td>
<td>laser_ctrl/blue_pwr_0_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>R12C2[2][B]</td>
<td style=" font-weight:bold;">laser_ctrl/blue_pwr_0_s0/Q</td>
</tr>
<tr>
<td>0.558</td>
<td>0.174</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C3</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s4/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C3</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s4/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C3</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s4</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.174, 41.295%; tC2Q: 0.247, 58.705%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_20_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_20_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R13C3[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_20_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C3[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_24_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R11C2[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_24_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_26_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_26_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R11C2[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_26_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_26_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_31_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_31_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R13C3[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_31_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C3[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C3[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_31_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_32_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C2[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_32_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R4C2[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_32_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C2[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R4C2[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R4C2[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_81_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_81_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R12C10[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_81_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C10[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_81_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_109_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C17[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_109_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R12C17[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_109_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C17[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C17[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C17[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_109_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_116_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C11[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_116_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R2C11[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_116_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C11[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R2C11[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R2C11[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_116_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_135_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_134_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_135_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R7C11[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_135_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_134_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R7C11[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_134_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R7C11[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_134_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.422</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.559</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_145_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_145_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R9C7[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_145_s0/Q</td>
</tr>
<tr>
<td>0.559</td>
<td>0.175</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C7[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C7[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C7[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_145_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.175, 41.492%; tC2Q: 0.247, 58.508%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.423</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.560</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/red_r1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/red_r2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C18[2][B]</td>
<td>laser_ctrl/red_r1_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R9C18[2][B]</td>
<td style=" font-weight:bold;">laser_ctrl/red_r1_s0/Q</td>
</tr>
<tr>
<td>0.560</td>
<td>0.176</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C18[2][A]</td>
<td style=" font-weight:bold;">laser_ctrl/red_r2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C18[2][A]</td>
<td>laser_ctrl/red_r2_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C18[2][A]</td>
<td>laser_ctrl/red_r2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.425</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.562</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/pwm_detect_inst/cycle_cnt_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_15_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C16[0][A]</td>
<td>laser_ctrl/pwm_detect_inst/cycle_cnt_15_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>8</td>
<td>R15C16[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/pwm_detect_inst/cycle_cnt_15_s0/Q</td>
</tr>
<tr>
<td>0.562</td>
<td>0.178</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C16[2][B]</td>
<td style=" font-weight:bold;">laser_ctrl/pwm_detect_inst/pwm_cycle_15_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R15C16[2][B]</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_15_s1/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R15C16[2][B]</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_15_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.178, 41.854%; tC2Q: 0.247, 58.146%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.428</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.564</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/en_r1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/en_r2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C19[0][A]</td>
<td>laser_ctrl/en_r1_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R9C19[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/en_r1_s0/Q</td>
</tr>
<tr>
<td>0.564</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C19[0][B]</td>
<td style=" font-weight:bold;">laser_ctrl/en_r2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C19[0][B]</td>
<td>laser_ctrl/en_r2_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C19[0][B]</td>
<td>laser_ctrl/en_r2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 42.242%; tC2Q: 0.247, 57.758%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.437</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.584</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s2</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/power_r0_0_s5</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C11[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s2/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>14</td>
<td>R17C11[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_6_s2/Q</td>
</tr>
<tr>
<td>0.584</td>
<td>0.201</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C12[1][A]</td>
<td style=" font-weight:bold;">laser_ctrl/power_r0_0_s5/CE</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R17C12[1][A]</td>
<td>laser_ctrl/power_r0_0_s5/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R17C12[1][A]</td>
<td>laser_ctrl/power_r0_0_s5</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.201, 44.828%; tC2Q: 0.247, 55.172%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.443</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.580</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C11[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R11C11[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_72_s0/Q</td>
</tr>
<tr>
<td>0.580</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C10[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.196, 44.283%; tC2Q: 0.247, 55.717%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.443</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.580</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_79_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_79_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R12C9[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_79_s0/Q</td>
</tr>
<tr>
<td>0.580</td>
<td>0.196</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C10[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.196, 44.283%; tC2Q: 0.247, 55.717%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.445</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.582</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/pwr_buf_1_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/ld1_pwr_buf_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C12[3][A]</td>
<td>laser_ctrl/pwr_buf_1_s0/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>4</td>
<td>R18C12[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/pwr_buf_1_s0/Q</td>
</tr>
<tr>
<td>0.582</td>
<td>0.198</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C14[3][A]</td>
<td style=" font-weight:bold;">laser_ctrl/ld1_pwr_buf_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C14[3][A]</td>
<td>laser_ctrl/ld1_pwr_buf_1_s0/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C14[3][A]</td>
<td>laser_ctrl/ld1_pwr_buf_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.198, 44.502%; tC2Q: 0.247, 55.498%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.661</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C19[0][A]</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>3</td>
<td>R6C19[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/alarm_ctrl/temp_cnt_5_s1/Q</td>
</tr>
<tr>
<td>0.386</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C19[0][A]</td>
<td>laser_ctrl/alarm_ctrl/n119_s3/I0</td>
</tr>
<tr>
<td>0.661</td>
<td>0.276</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R6C19[0][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/alarm_ctrl/n119_s3/F</td>
</tr>
<tr>
<td>0.661</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R6C19[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/alarm_ctrl/temp_cnt_5_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C19[0][A]</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C19[0][A]</td>
<td>laser_ctrl/alarm_ctrl/temp_cnt_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>0.661</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.137</td>
</tr>
<tr>
<td class="label">From</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[0][A]</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>0.384</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R3C17[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/alarm_ctrl/pd_cnt_6_s1/Q</td>
</tr>
<tr>
<td>0.386</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[0][A]</td>
<td>laser_ctrl/alarm_ctrl/n21_s1/I2</td>
</tr>
<tr>
<td>0.661</td>
<td>0.276</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R3C17[0][A]</td>
<td style=" background: #97FFFF;">laser_ctrl/alarm_ctrl/n21_s1/F</td>
</tr>
<tr>
<td>0.661</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C17[0][A]</td>
<td style=" font-weight:bold;">laser_ctrl/alarm_ctrl/pd_cnt_6_s1/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C17[0][A]</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1/CLK</td>
</tr>
<tr>
<td>0.137</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C17[0][A]</td>
<td>laser_ctrl/alarm_ctrl/pd_cnt_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.492</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.967</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C4[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK</td>
</tr>
<tr>
<td>2.214</td>
<td>0.247</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>R18C4[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/word_count_7_s0/Q</td>
</tr>
<tr>
<td>2.216</td>
<td>0.002</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C4[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/I1</td>
</tr>
<tr>
<td>2.492</td>
<td>0.276</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>R18C4[1][A]</td>
<td style=" background: #97FFFF;">gw_gao_inst_0/u_la0_top/data_to_word_counter_7_s0/F</td>
</tr>
<tr>
<td>2.492</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R18C4[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/word_count_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>0.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>0.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>1.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>1.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R18C4[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0/CLK</td>
</tr>
<tr>
<td>1.967</td>
<td>0.000</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R18C4[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/word_count_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>2</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C5[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C5[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C5[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C6[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C6[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C6[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C5[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C5[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C5[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C5[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C5[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C5[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C5[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C5[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C5[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C5[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C5[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C5[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C5[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C5[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C5[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C5[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C5[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C5[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R11C5[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C5[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R11C5[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R13C6[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R13C6[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>2.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.489</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.149</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.534</td>
<td>0.340</td>
<td>tC2Q</td>
<td>FF</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>7.489</td>
<td>1.955</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R12C7[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.181</td>
<td>0.181</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C7[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK</td>
</tr>
<tr>
<td>10.149</td>
<td>-0.032</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R12C7[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.014</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.195, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.955, 85.201%; tC2Q: 0.340, 14.799%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.181, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.283</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>56.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>52.008</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>55.000</td>
<td>55.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>55.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>55.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>56.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C2[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>50.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>50.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>51.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>51.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C2[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0/CLK</td>
</tr>
<tr>
<td>51.997</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
<tr>
<td>52.008</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C2[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.822</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.691</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>56.699</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>52.008</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>55.000</td>
<td>55.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>55.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>55.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>56.699</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>50.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>50.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>51.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>51.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0/CLK</td>
</tr>
<tr>
<td>51.997</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
<tr>
<td>52.008</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C8[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.822</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 84.105%; tC2Q: 0.247, 15.895%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.691</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>56.699</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>52.008</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>tck_pad_i:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>55.000</td>
<td>55.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>55.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>55.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>55.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>56.699</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>50.000</td>
<td>50.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>tck_pad_i</td>
</tr>
<tr>
<td>50.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/I</td>
</tr>
<tr>
<td>50.626</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>IOT9[A]</td>
<td>gw_gao_inst_0/tck_ibuf/O</td>
</tr>
<tr>
<td>50.626</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_pad_i</td>
</tr>
<tr>
<td>51.251</td>
<td>0.626</td>
<td>tINS</td>
<td>RR</td>
<td>466</td>
<td>-</td>
<td>gw_gao_inst_0/u_gw_jtag/tck_o</td>
</tr>
<tr>
<td>51.967</td>
<td>0.716</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R9C8[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0/CLK</td>
</tr>
<tr>
<td>51.997</td>
<td>0.030</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
<tr>
<td>52.008</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R9C8[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_tck_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>1.822</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 84.105%; tC2Q: 0.247, 15.895%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 1.251, 63.613%; route: 0.716, 36.387%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.847</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.995</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>5.995</td>
<td>0.603</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C7[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R5C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R5C7[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.603, 70.955%; tC2Q: 0.247, 29.045%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C4[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C4[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_dly_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C3[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C3[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C3[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_end_dly_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C3[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C3[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C3[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.144</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.292</td>
<td>0.900</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C4[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C4[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.900, 78.463%; tC2Q: 0.247, 21.537%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C3[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C2[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C3[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C3[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C2[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R3C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R3C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.148</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.296</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.296</td>
<td>0.904</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R6C3[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R6C3[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.904, 78.549%; tC2Q: 0.247, 21.451%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.339</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.487</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.487</td>
<td>1.095</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C2[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C2[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.095, 81.599%; tC2Q: 0.247, 18.401%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.503</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.503</td>
<td>1.112</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C6[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C6[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C6[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.112, 81.819%; tC2Q: 0.247, 18.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.503</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.503</td>
<td>1.112</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R14C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R14C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.112, 81.819%; tC2Q: 0.247, 18.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.503</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.503</td>
<td>1.112</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C8[3][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R12C8[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R12C8[3][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.112, 81.819%; tC2Q: 0.247, 18.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.503</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.503</td>
<td>1.112</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C7[2][B]</td>
<td>gw_gao_inst_0/u_la0_top/trigger_seq_start_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.112, 81.819%; tC2Q: 0.247, 18.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.355</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.503</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.503</td>
<td>1.112</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/triger_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C7[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C7[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/triger_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.112, 81.819%; tC2Q: 0.247, 18.181%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.365</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.513</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.513</td>
<td>1.121</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.121, 81.941%; tC2Q: 0.247, 18.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.365</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.513</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.513</td>
<td>1.121</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R13C6[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.121, 81.941%; tC2Q: 0.247, 18.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.365</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>6.513</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>0.148</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>sys_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>sys_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>5.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.145</td>
<td>0.145</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R3C9[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK</td>
</tr>
<tr>
<td>5.392</td>
<td>0.247</td>
<td>tC2Q</td>
<td>FR</td>
<td>47</td>
<td>R3C9[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s1/Q</td>
</tr>
<tr>
<td>6.513</td>
<td>1.121</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>803</td>
<td>PLL_L</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>0.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK</td>
</tr>
<tr>
<td>0.148</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R11C6[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.008</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>-5.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.145, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.121, 81.941%; tC2Q: 0.247, 18.059%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.137, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/start_reg_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_133_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_133_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_133_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_74_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_142_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>laser_ctrl/pwm_detect_inst/pwm_high_15_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>laser_ctrl/pwm_detect_inst/pwm_high_15_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>laser_ctrl/pwm_detect_inst/pwm_high_15_s1/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>4.016</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.942</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>0.926</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>sys_clk</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_0_s1</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>5.195</td>
<td>0.195</td>
<td>tNET</td>
<td>FF</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_0_s1/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td>sys_clk</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>pll/pllo_inst/CLKOUTA</td>
</tr>
<tr>
<td>10.137</td>
<td>0.137</td>
<td>tNET</td>
<td>RR</td>
<td>laser_ctrl/pwm_detect_inst/pwm_cycle_0_s1/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>803</td>
<td>DAC3_CLK_d</td>
<td>0.012</td>
<td>0.490</td>
</tr>
<tr>
<td>466</td>
<td>control0[0]</td>
<td>0.567</td>
<td>1.279</td>
</tr>
<tr>
<td>168</td>
<td>n20_3</td>
<td>45.904</td>
<td>1.825</td>
</tr>
<tr>
<td>147</td>
<td>data_out_shift_reg_145_9</td>
<td>42.730</td>
<td>2.184</td>
</tr>
<tr>
<td>144</td>
<td>n1242_17</td>
<td>38.754</td>
<td>4.142</td>
</tr>
<tr>
<td>108</td>
<td>n1242_15</td>
<td>39.975</td>
<td>3.430</td>
</tr>
<tr>
<td>62</td>
<td>n698_13</td>
<td>5.228</td>
<td>1.042</td>
</tr>
<tr>
<td>59</td>
<td>dividend_temp_58_9</td>
<td>5.807</td>
<td>1.360</td>
</tr>
<tr>
<td>47</td>
<td>rst_ao</td>
<td>2.659</td>
<td>2.300</td>
</tr>
<tr>
<td>37</td>
<td>op_reg_en</td>
<td>41.099</td>
<td>1.012</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R2C5</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C9</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C10</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C11</td>
<td>100.00%</td>
</tr>
<tr>
<td>R2C12</td>
<td>100.00%</td>
</tr>
<tr>
<td>R4C5</td>
<td>100.00%</td>
</tr>
<tr>
<td>R13C17</td>
<td>100.00%</td>
</tr>
<tr>
<td>R4C4</td>
<td>100.00%</td>
</tr>
<tr>
<td>R7C4</td>
<td>100.00%</td>
</tr>
<tr>
<td>R7C5</td>
<td>100.00%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name clk_in -period 20 -waveform {0 10} [get_ports {clk_in}] -add</td>
</tr>
<tr>
<td>TC_GENERATED_CLOCK</td>
<td>Actived</td>
<td>create_generated_clock -name sys_clk -source [get_ports {clk_in}] -master_clock clk_in -multiply_by 2 -duty_cycle 50 -add [get_pins {pll/pllo_inst/CLKOUTA}]</td>
</tr>
</table>
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